Next, we link the object files together to generate the executable main. So next we compile these files separately. o files and then link them into executable named main.

h files, we need to compile these files separately to generate. Square.cpp: CPP implementation file for square class.Point.cpp: CPP implementation file for point class.Example Of Make And MakefileĬonsider a program example with the following files: The measure advantage of this variation of the makefile is that we just need to change the values of the variables that we have used whenever there is some change in the compiler, compiler flags, or executable program name. The third variable ‘TARGET’ contains the name of the program for which we need to build the executable.

Another variable ‘CFLAGS’ contains the compiler flags that we will use. # -Wall - this flag is used to turn on most compiler warningsĪs shown in the above example, in this makefile we make use of the variable ‘CC’ that contains the compiler value that we are using (GCC in this case). # -g - this flag adds debugging information to the executable file # the compiler: gcc for C program, define as g++ for C++ Let’s see another variation of the makefile. The second target label ‘clean’ removes all the files with the name ‘myprogram’. In the above makefile, we have specified two target labels, first is the label ‘all’ to build executable from myprogram and mylib object files. # a build command to build myprogram executable from myprogram.o and mylib.lib

# (note: the in the command line is necessary for make to work)Ī simple example of the makefile is shown below. So a generic makefile is as shown below: # comment We can also have a set of target entries for executing a set of commands specified by the target label. o or other executable files in C or C++ and. Now let’s see the general structure of makefile.Ī makefile typically starts with variable declarations followed by a set of target entries for building specific targets. A makefile also contains information like source-level dependencies for each file as well as the build-order dependencies. %make clean #here clean is a target_label specified for rm commands C++ MakefileĪ makefile is nothing but a text file that is used or referenced by the ‘make’ command to build the targets. The general syntax of make is: %make target_label #target_label is a specific target in makefileįor example, if we want to execute rm commands to clean up files, we write: The make command is used in the makefile to build modules or to clean up the files. The make tool reads all these rules and behaves accordingly.įor example, if a rule specifies any dependency, then the make tool will include that dependency for compilation purposes. There are various rules that are specified as target entries in the makefile. Make is a UNIX tool and is used as a tool to simplify building executable from different modules of a project.

How to compile c++ on mac